|In order to meet stringent power budgets, current IoT devices often have limited processing power and, for more complex operations, upload sensor data to cloud servers for analysis. This introduces unavoidable latencies potentially prejudicing timely responses to significant incidents. In addition, this operational model mandates robust and secure connectivity provision without which the device’s usefulness can be compromised.
Critical to resolving this challenge is to dramatically improve power efficiency in order to shift AI inference processing to the edge. However, this demands significant increases in both computational capability as well as on-chip memory requirements. The key to achieving target performance goals is predicated on the ability to rapidly execute relatively simple data manipulation operations. Implementing these in a classic “fetch-process-store” type scenario adversely impacts power consumption because not only is the processor and SRAM consuming power but the data must be shifted from, and then back to memory.
SureCore has exploited its expertise in ultra-low power memory design to create CompuRAM, an IMC development platform dedicated to enabling the realisation of specific computation and data manipulation capabilities within a low power SRAM implementation thereby facilitating significant power savings.
The white paper introduces sureCore’s approach to IMC and is available to download from https://www.sure-core.com/technology/ . There is also an interview with Tony Stansfield, sureCore’s CTO, on https://semiwiki.com/podcast/podcast-ep111-how-surecore-is-fueling-the-ai-revolution-with-tony-stansfield/