Intel Custom Foundry Certifies Cadence Implementation and Signoff Tools for 10nm Tri-Gate Process

Intel Custom Foundry Certifies Cadence Implementation and Signoff Tools for 10nm Tri-Gate Process


Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its implementation and signoff tools have achieved certification on the Intel® third-generation 10nm tri-gate process for customers of Intel Custom Foundry. Intel Custom Foundry utilized a PowerVR GT7200 graphics processing unit (GPU) from Imagination Technologies as part of the certification process.

The tool certification and enablement provide Intel Custom Foundry customers with a complete and integrated system-on-chip (SoC) design flow. Cadence® tools in the flow include:

Innovus™ Implementation System: This massively parallel physical implementation system utilizes GigaPlace™ placement technology, GigaOpt™ optimization technology and integrated color-/pin-access-/variability–aware routing and timing closure to deliver high-quality designs with competitive power, performance and area (PPA) targets while accelerating time to market.

Quantus™ QRC Extraction Solution: This solution uses a single Intel Custom Foundry-certified techfile and delivers a faster, scalable solution by supporting both cell-level and transistor-level extractions during design implementation and signoff with best-in-class accuracy versus foundry golden.

Tempus™ Timing Signoff Solution: This massively parallelized timing signoff solution provides full-chip static timing analysis (STA) with gate-level delay calculation including signal integrity (SI) analysis, advanced on-chip variation analysis, advanced-node functionality required for double-patterning and waveform effects, and optimization for timing and leakage power.

Voltus™ IC Power Integrity Solution: This cell-level power integrity solution supports comprehensive electromigration and IR-drop (EM/IR) design rules and requirements while providing full-chip system-on-chip (SoC) power signoff accuracy.

Voltus-Fi Custom Power Integrity Solution: This transistor-level power integrity solution supports comprehensive EM/IR design rules and requirements while providing SPICE-level power signoff accuracy for analog, memory and custom digital IP blocks.

Spectre® Classic Simulator, Spectre Accelerated Parallel Simulator (APS) and Spectre RF Simulation: These products deliver fast and accurate circuit simulation of complex analog, radio frequency (RF) and mixed-signal circuits with full support for advanced-node device models and parasitics.

For more information on the Cadence tools that are certified, please visit http://www.cadence.com/news/icf10nm, and for more information on Intel Custom Foundry, please visit http://www.intel.com/foundry.

 

Please click the link below to download the latest press release from Cadence Design Systems, CA239:

http://download.publitek.com/CA239(A)Cadence_ICF_10nm_Press_Release_INTEL_and_IMG_Approved_FINAL.docx

or visit the Cadence website:
https://www.cadence.com/content/cadence-www/global/en_US/home/company/newsroom/press-releases/pr/2016/intel-custom-foundry-certifies-cadence-implementation-and-signof.html

 

 

Cadence Design Systems GmbH
Andrea Huse
Tel: +49 (0) 89 4563 1726
Email: ahuse@cadence.com