- Cadence digital, signoff and custom/analog tools certified and PDK-enabled for latest 7nm DRM and SPICE
- TSMC and Cadence address custom and mixed-signal design requirements at advanced-process nodes through delivery of 7nm Custom Design Reference Flow
- Cadence 7nm library characterization tool flow enables accurate process variation signoff for ultra-low-voltage applications
- Cadence 7nm high-speed SerDes and low-latency DDR IP delivered in active customer engagements
SAN JOSE, Calif., September 22, 2016—Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced several important deliveries in its collaboration with TSMC to advance 7nm FinFET designs for mobile and high-performance computing (HPC) platforms. As a result of the joint work, Cadence® digital, signoff and custom/analog tools have achieved certification for the latest Design Rule Manual (DRM) and SPICE for the TSMC 7nm process. In addition, a new process design kit (PDK) enabling customers to achieve optimal power, performance and area (PPA) is now available. Cadence has also made enhancements to the 7nm Custom Design Reference Flow and library characterization flow. These design tool advancements have enabled Cadence to accelerate initial deliveries of its high-speed SerDes and low-latency DDR IP cores to leading customers, with test chips expected to tape out in the fourth quarter of this year. These products represent the first of a comprehensive portfolio of application-optimized 7nm solutions to be developed by Cadence.
To learn more about the Cadence digital and signoff advanced node solutions, please visit www.cadence.com/go/tsmc7nmds. For information on the Cadence custom/analog advanced node solutions, visit www.cadence.com/go/tsmc7nmca. For information on Cadence IP advanced node solutions, please visit www.cadence.com/go/tsmc7nmip.
7nm Tool Certification
TSMC and Cadence have collaborated on an integrated flow based on tool certification targeting TSMC’s 7nm mobile and HPC platforms. The integrated flow ensures that the certified tools work seamlessly when used together.
Cadence provides a fully integrated and stable TSMC 7nm flow, from implementation to final signoff. The digital implementation and signoff tools certified include Innovus™ Implementation System, Quantus™ QRC Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, Physical Verification System and Layout-Dependent Effect (LDE) Electrical Analyzer. Support for the 7nm mobile and HPC platform, available in November 2016, includes via-pillar and clock mesh handling and bus routing, as well as support for the high-performance library to deliver targeted PPA and mitigated electro-migration (EM), which enable customers to reduce iterations and achieve their cost and performance objectives. In addition, both companies are working on enabling via pillar what-if analysis in Genus™ Synthesis Solution and continuing to optimize pin access and cut metal handling in Innovus Implementation System.
The certified custom/analog tools include Spectre® Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS) and Spectre Circuit Simulator, as well as the Virtuoso® custom IC advanced-node platform. The Spectre suite delivers circuit simulation to support advanced-node device models with self-heating and reliability effects. The Virtuoso suite is further optimized for 7nm custom design implementation and provides innovative in-design to signoff flows.
7nm CDRF Enhancements
TSMC and Cadence are also addressing custom and mixed-signal design requirements at advanced-process nodes through delivery of the 7nm Custom Design Reference Flow (CDRF). The CDRF introduces advanced methodologies and features for productivity improvements, electrical analysis for better predictability and design closure, and higher quality of silicon. The CDRF consists of multiple in-depth “how-to” modules on topics such as mixed-signal functional verification, yield optimization and reliability analysis, construction of FinFET arrays to avoid density gradient effects (DGE), LDE-aware analysis, and color-aware electrical analysis.
7nm Library Characterization Tool Flow Enhancements
In addition to the tools certified for TSMC’s 7nm process, the Virtuoso Liberate™ Characterization Solution and the Virtuoso Variety™ Statistical Characterization Solution have been enhanced to deliver Liberty libraries, including advanced timing, noise and power models. The solutions utilized innovative methods to characterize Liberty Variation Format (LVF) models enabling process variation signoff for ultra-low-voltage applications and to create EM models enabling signal EM optimizations and signoff.
Optimized 7nm IP Development
Working together, Cadence and TSMC have developed some of the first design IP offerings for the 7nm process, offering early IP access to protocols that are optimized for and most relevant to mobile and HPC applications. Simulations of Cadence’s high-speed SerDes and low-latency DDR IP initial customer deliveries indicate a 50 percent power reduction and a 35 percent speed gain compared to TSMC’s 16nm process technology. These early 7nm SerDes and DDR deliveries represent the first of a comprehensive portfolio of Cadence 7nm solutions.
“TSMC’s process innovations require ongoing tool and IP enhancements so that we can deliver optimal solutions for advanced-node customers,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Our joint work supports the needs of early customers who are transitioning to the 7nm node to maintain leadership in the mobile and HPC markets.”
“We worked closely with Cadence to certify the tools and integrated flow for 7nm designs, which will help customers achieve PPA objectives and create designs with confidence,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “By working together with Cadence, we are able to actively engage with customers on advanced 7nm designs to enable them to maximize the benefits of this leading-edge technology.”